ARAS: Asynchronous RISC Architecture Simulator1

نویسندگان

  • Chia-Hsing Chien
  • Mark A. Franklin
  • Tienyo Pan
  • Prithvi Prabhu
چکیده

In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this sim-ulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline connguration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, the pipeline connguration can be altered to improve its performance. Thus, one can explore the design space of asynchronous pipeline architectures.

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تاریخ انتشار 1994